/*=============================================================================
# FileName    : lcd_top.v
# Author      : author
# Email       : email@email.com
# Description :
# Version     : 1.0
# LastChange  : 2016-03-28 17:34:32
# ChangeLog   :
=============================================================================*/

`timescale  1 ns/1 ps

module lcd(
		input			clk,
		input			rst,
	 
		output	reg	[3:0]	led,           //LED

		input	wire		JTCK          ,
		input	wire		JTRST_n       ,
		input	wire		JTDI          ,
		input	wire		JTMS          ,
		output	wire		JTDO          ,	
	 
	 	//////////////// FLASH PIN 
		output	wire		FLASH_SCK     ,	
		output	wire		FLASH_CS_n    ,	
		inout   tri             FLASH_IO0_SI  ,	
		inout   tri             FLASH_IO1_SO  ,
		
		output	wire	[7:0]	port_a,
	
		output		[31:0]	tout  	
		);




wire	[31:0]	core_tout;
reg [31:0] counter;

always@(posedge clk or negedge rst)

begin
		if(!rst)
			begin
				counter <= 0;
			end
		else
				counter <= counter+1;
end

always@(posedge clk or negedge rst)

begin
		if(!rst)
			begin
				led <= 4'b0000;
			end
		else
			begin
				case(counter[27:25])
					0:		led <= 4'b1110;
					1:		led <= 4'b1101;
					2:		led <= 4'b1011;
					3:		led <= 4'b0111;
					4:		led <= 4'b1100;
					5:		led <= 4'b0011;
					6:		led <= 4'b0110;
					7:		led <= 4'b1001;
				endcase
			end
end


// wire  resetb_mcu;
// assign resetb_mcu = resetb || (start_state != START_OK);


wire  FLASH_IO0_SI_o           ;
wire  FLASH_IO0_SI_i         ;
wire  FLASH_SI_OE            ;

wire  FLASH_IO1_SO_o           ;
wire  FLASH_IO1_SO_i         ;
wire  FLASH_SO_OE            ;
    
assign FLASH_IO0_SI_i = FLASH_IO0_SI;
assign FLASH_IO0_SI = FLASH_SI_OE ?   FLASH_IO0_SI_o : 1'bz   ;

assign FLASH_IO1_SO_i = FLASH_IO1_SO;
assign FLASH_IO1_SO = FLASH_SO_OE ?  FLASH_IO1_SO_o : 1'bZ ;

///////////////////////////////////////////////////////////////
alta_mcu_top    alta_mcu_topEx01
(
    .CLK                    (     clk_62_5m                 ),
    .POR_n                  (     resetb                    ),               //(     resetb_mcu      ),
    .EXT_CPU_RST_n          (     1'b1                      ),
    .UART_RXD               (                               ),
    .UART_CTS_n             (                               ),
    .UART_TXD               (                               ),
    .UART_RTS_n             (                               ),
    .JTRST_n                (    1'b1                       ),  //(    resetb                     ),     //(    1'b1                       ),  //(        test_out0              ),        //(    JTRST_n          ),
    .JTCK                   (    JTCK                       ),
    .JTDI                   (    JTDI                       ),
    .JTMS                   (    JTMS                       ),
    .JTDO                   (    JTDO                       ),
    .EXT_RAM_EN             (    1'b0                       ),
    .EXT_RAM_WR             (                     ),
    .EXT_RAM_ADDR           (                   ),
    .EXT_RAM_BYTE_EN        (                ),
    .EXT_RAM_WDATA          (                  ),
    .EXT_RAM_RDATA          (                  ),
    .HRESP_EXT              (  2'b00                         ),
//    .HREADY_OUT_EXT         (   hready_out                  ),
//    .HRDATA_EXT             (   hrdata                      ),
//    .HTRANS_EXT             (   htrans                      ),
//    .HADDR_EXT              (   haddr                       ),
//    .HWRITE_EXT             (   hwrite                      ),
//   .HSEL_EXT               (   hsel                        ),
//    .HWDATA_EXT             (   hwdata                      ),
//    .HSIZE_EXT              (   hsize                       ),
//    .HREADY_IN_EXT          (   hready_in                   ),

    // .FLASH_BIAS             (    FLASH_BIAS           ),
    .FLASH_SCK              (        flash_SCK              ),
    .FLASH_CS_n             (        flash_CS_n             ),

    .FLASH_BIAS             ( 24'hB1CE6                     ),

    .FLASH_IO0_SI           (   FLASH_IO0_SI_o                ), //(   FLASH_IO0_SI                ),  //(   flash_SI                    ),
    .FLASH_IO0_SI_i         (   FLASH_IO0_SI_i              ),
    .FLASH_SI_OE            (   flash_si_oe                 ),

    .FLASH_IO1_SO           (   FLASH_IO1_SO_o                ),
    .FLASH_IO1_SO_i         (   FLASH_IO1_SO_i              ), //(   FLASH_IO1_SO_i              ), //(    flash_SO                   ),
    .FLASH_SO_OE            (   FLASH_SO_OE                 ),

    .FLASH_IO2_WPn          (                               ),
    .FLASH_IO2_WPn_i        (       1'b1                    ),
    .WPn_IO2_OE             (                               ),

    .FLASH_IO3_HOLDn        (                               ),
    .FLASH_IO3_HOLDn_i      (       1'b1                    ),
    .HOLDn_IO3_OE           (                               ),

   //.GPIO0_I                ( GPIO0_I          ),
   //.GPIO0_O                ( GPIO0_O          ),
   //.nGPEN0                 ( nGPEN0           ),
   //.GPIO1_I                ( GPIO1_I          ),
   //.GPIO1_O                ( GPIO1_O          ),
   //.nGPEN1                 ( nGPEN1           ),
   //.GPIO2_I                ( GPIO2_I          ),
   //.GPIO2_O                ( GPIO2_O          ),
   //.nGPEN2                 ( nGPEN2           ),
   //.O_INI_IP               ( O_INI_IP         )
) ;


assign tout = core_tout;

endmodule
